Open Agila: Architecture, Ada & V

Module 2 – Ports and language interoperability

Page 1 of 3 · About 15 minutes per lesson, including practice.

Trace a bounded queue in V

15-minute session: read for 3 minutes, trace for 3, experiment for 7, and complete the check for 2. Spend longer whenever you need.

This single-file V model accepts four values and rejects a fifth. The real Ada port uses a fixed ring buffer. The model teaches capacity; it does not implement permissions or kernel IPC. Run it in the browser, then change capacity and predict the new output.

Your experiment

Set capacity to zero, then to five. Explain the accepted count in each case. Compare the array model with the fixed storage in agila_ports.ads.

fn main() {
    capacity := 4
    mut queue := []u32{}
    for value in 1 .. 6 {
        if queue.len >= capacity { println('Full'); continue }
        queue << u32(value)
    }
    println(queue.len)
}

Expected result: Full 4

Practice and evidence

Keep three notes: your prediction, the actual result, and why they match or differ. The completion check grades understanding; the practice task builds skill.

Language reference

Example code on Agila Forge ↗